The invention is in the field of Semiconductor-On-Insulator (SOI) devices, and relates more particularly to SOI JFET devices suitable for high-voltage applications.
In fabricating high-voltage power devices, tradeoffs and compromises must typically be made in areas such as breakdown voltage, size, "on" resistance and manufacturing simplicity and reliability. Frequently, improving one parameter, such as breakdown voltage, will result in the degradation of another parameter, such as "on" resistance. Ideally, such devices would feature superior characteristics in all areas, with a minimum of operational and fabrication drawbacks.
One particularly advantageous form of lateral thin-film SOI device includes a semiconductor substrate, a buried insulating layer on the substrate, and a lateral MOS device on the buried insulating layer, the MOS device, such as a MOSFET, including a semiconductor surface layer on the buried insulating layer and having a source region of a first conductivity type formed in a body region of a second conductivity type opposite to that of the first, an insulated gate electrode over a channel region of the body region and insulated therefrom by an insulation region, a lateral drift region of the first conductivity type, and a drain region of the first conductivity type laterally spaced apart from the channel region by the drift region.
A device of this type is shown in FIG. 1 common to related U.S. Pat. No. 5,246,870 (directed to a method) and U.S. Pat. No. 5,412,241 (directed to a device), commonly-assigned with the instant application and incorporated herein by reference. The device shown in FIG. 1 of the aforementioned patents is a lateral SOI MOSFET device having various features, such as a thinned SOI layer with a linear lateral doping profile in the drift region and an overlying field plate, to enhance operation. As is conventional, this device is an n-channel or NMOS transistor, with n-type source and drain regions, manufactured using a process conventionally referred to as NMOS technology. An SOI device with a linearly-doped drift region of constant thickness is shown in U.S. Pat. No. 5,300,448, also commonly-assigned with the instant application and incorporated herein by reference.
More advanced techniques for enhancing high-voltage and high-current performance parameters of SOI power devices are shown in U.S. patent application Ser. No. 08/998,048, filed Dec. 24, 1997, commonly-assigned with the instant application and incorporated herein by reference. Another technique for improving the performance of an SOI device is to form a hybrid device, which combines more than one type of device configuration into a single structure. Thus, for example, in U.S. patent application Ser. No. 09/122,407, filed Jul. 24, 1998, commonly-assigned with the instant application and incorporated herein by reference, an SOI device is disclosed which includes a lateral DMOS transistor and an LIGB transistor in the same structure.
Thus, it will be apparent that numerous techniques and approaches have been used in order to enhance the performance of MOS power semiconductor devices, in an ongoing effort to attain a more nearly optimum combination of such parameters as breakdown voltage, size, current-carrying capability and manufacturing ease. While all of the foregoing structures provide varying levels of improvement in device performance, no one device or structure fully optimizes all of the design requirements for high-voltage, high-current operation.
Although the references discussed above relate to MOS transistor devices, in some applications it would be desirable to have high-voltage SOI JFET device structures which exhibit similarly enhanced performance. Although SOI JFET devices presently exist, as shown for example in U.S. Pat. Nos. 5,130,770 and 5,432,377, these devices do not exhibit the type of superior high-voltage, high-current performance as exemplified by the SOI MOS devices discussed above.
Accordingly, it would be desirable to have an SOI JFET device structure, preferably of the normally "on" type, capable of high performance in a high-voltage, high-current environment, in which operating parameters, and in particular "on" resistance and breakdown voltage, are further optimized.
It would also be desirable to have an SOI JFET device structure which can be fabricated using a process technology very similar to that used to fabricate enhanced SOI MOSFET devices such as those discussed above.